module Uart_Bps_Module
(
	CLK_50M,RST_N,bps_start,
	bps_flag
);

input		CLK_50M;			
input		RST_N;				
input 		bps_start;			
output 		bps_flag;			

reg		[12:0] 	time_cnt;			
reg		[12:0] 	time_cnt_n;				
reg				bps_flag;			
reg				bps_flag_n;				


parameter		BPS_PARA   = 9'd434;	//波特率: 50M / 434 = 115200
parameter 		BPS_PARA_2 = 8'd217;

always @ (posedge CLK_50M or negedge RST_N)
begin	
	if(!RST_N)							
		time_cnt <= 13'b0;				
	else
		time_cnt <= time_cnt_n;			
end


always @ (*)
begin
	if((time_cnt == BPS_PARA) || (!bps_start)) 
		time_cnt_n = 1'b0;				
	else	
		time_cnt_n = time_cnt + 1'b1;	
end

always @ (posedge CLK_50M or negedge RST_N)
begin
	if(!RST_N)								
		bps_flag <= 1'b0;					
	else
		bps_flag <= bps_flag_n;			
end


always @ (*)
begin
	if(time_cnt == BPS_PARA_2)				
		bps_flag_n = 1'b1;				
	else
		bps_flag_n = 1'b0;			
end

endmodule

